1. Field of the Invention
The present invention relates to a transistor and a method of fabricating the same, and more particularly, it relates to an improvement for compatibly improving an output characteristic and an OFF characteristic.
2. Discussion of the Background
In general, a MOSFET (hereinafter simply referred to as MOS) has been mainly employed in a region having a rated voltage of not more than 200 V and a bipolar transistor (hereinafter simply referred to as BIP) or an insulated gate bipolar transistor (hereinafter simply referred to as IGBT) has been employed in a region of at least 300 V in various types of power transistors (power transistors). The respective ones of the conventional MOS, BIP and IGBT are now described.
FIG. 37 is a sectional view showing the structure of the conventional MOS. This MOS 151 corresponds to an example of the so-called vertical MOS. As shown in FIG. 37, an n.sup.- layer 172 is formed on an N.sup.+ layer 171 in the MOS 151, and p-type base layers 173 are selectively formed in an upper surface part of the n.sup.- layer 172 by diffusing a p-type impurity. Further, n-type source regions 174 are selectively formed in upper surface parts of the base layers 173 by diffusing an n-type impurity. The source layers 174 are partially arranged in single base layers 173, and the impurity concentrations thereof are set higher than the n.sup.- layer 172.
A gate oxide film 177 is formed on an exposed surface of the n.sup.- layer 172 and exposed surfaces of the base layers 173 held between the n.sup.- layer 172 and the source layers 174, and a gate electrode 178 made of polysilicon is formed further on this gate oxide film 177. Parts of the base layers 173 opposed to the gate electrode 178 through the gate oxide film 177 function as channel regions 176.
A source electrode 180 is formed on the exposed surfaces of the base layers 173 excluding the channel regions 176, i.e., upper surfaces of regions held between the source layers 174. The source electrode 180 and the gate electrode 178 are typically isolated from each other by an interlayer isolation film 179. Further, a drain electrode 182 is formed on an exposed surface of the N.sup.+ layer 171. These source electrode 180 and drain electrode 182 form a pair of main electrodes functioning as paths of a main current.
This MOS 51 operates as follows: First, a drain voltage V.sub.DS of prescribed magnitude is applied between the drain electrode 182 and the source electrode 180, so that the side of the drain electrode 182 is positive. When applying a gate voltage V.sub.GE (i.e., turning on a gate) exceeding a gate threshold voltage V.sub.GE (th) between the gate electrode 178 and the source electrode 180 so that the side of the gate electrode 178 is positive in this state, the p-type channel regions 176 are inverted to an n type and n-type channels are formed in the channel regions 176. Consequently, the n.sup.- layer 172 and the source layers 174 conduct with each other, whereby the drain electrode 182 and the source electrode 180 conduct with each other. Namely, the MOS 151 enters an ON state.
Then, when inverting the gate voltage V.sub.GE from the positive value to the value of zero or a negative (reverse bias) value (i.e., turning off the gate) in the state applying the drain voltage V.sub.DS, the channel regions 176 having been inverted to the n type return to the original p type. Consequently, the n.sup.- layer 172 and the source layers 174 are disconnected from each other, whereby the drain electrode 182 and the source electrode 180 are disconnected from each other. Namely, the MOS 151 enters an OFF state.
FIG. 38 is a sectional view showing the structure of the conventional BIP. In this BIP 152, an n.sup.- layer 202 is formed on an N.sup.+ layer 201, and a p-type base layer 203 is formed on an upper surface of the n.sup.- layer 202 by diffusing a p-type impurity. Further, an n-type emitter layer 204 is selectively formed in an upper surface part of the base layer 203 by diffusing an n-type impurity. The impurity concentration of the emitter layer 204 is set higher than the n.sup.- layer 202.
An emitter electrode 210 and a base electrode 211 are formed on exposed surfaces of the emitter layer 204 and the base layer 203 respectively, and a collector electrode 212 is formed on an exposed surface of the N.sup.+ layer 201. The collector electrode 212 and the emitter electrode 210 function as a pair of main electrodes.
This BIP 152 operates as follows: First, a collector voltage V.sub.CE of prescribed magnitude is applied between the collector electrode 212 and the emitter electrode 210 so that the side of the collector electrode 212 is positive. When supplying a base current from the base electrode 211 in this state, the diffusion potential of the base layer 203 is relaxed or canceled. Consequently, the collector electrode 212 and the emitter electrode 210 conduct with each other. Namely, the BIP 152 enters an ON state.
Then, when stopping supply of the base current in the state applying the collector voltage V.sub.CE, the diffusion potential of the base layer 203 revives. Consequently, the collector electrode 212 and the emitter electrode 210 are disconnected from each other. Namely, the BIP 152 enters an OFF state.
FIG. 39 is a sectional view showing the structure of the conventional IGBT. In this IGBT 153, an N.sup.+ buffer layer 311 is formed on a p.sup.+ layer 301, and an n.sup.- layer 302 is formed on the N.sup.+ buffer layer 311. Further, p-type base layers 303 are selectively formed in an upper surface part of the n.sup.- layer 302 by diffusing a p-type impurity. In addition, n-type emitter layers 304 are selectively formed in upper surface parts of the base layers 303 by diffusing an n-type impurity. The emitter layers 304 are partially arranged in single base layers 303, and the impurity concentrations thereof are set higher than the n.sup.- layer 302.
A gate oxide film 307 is formed on an exposed surface of the n.sup.- layer 302 and exposed surfaces of the base layers 303 held between the n.sup.- layer 302 and the emitter layers 304, and a gate electrode 308 made of polysilicon is formed further on this gate oxide film 307. Parts of the base layers 303 opposed to the gate electrode 308 through the gate oxide film 307 function as channel regions 306.
An emitter electrode 310 is formed on exposed surfaces of the base layers 303, i.e., upper surfaces of regions held between the emitter layers 304. The emitter electrode 310 and the gate electrode 308 are electrically isolated from each other by an interlayer isolation film 309. A collector electrode 312 is formed on an exposed surface of the p.sup.+ layer 301. These emitter electrode 310 and collector electrode 312 form a pair of main electrodes functioning as paths for a main current.
As hereinabove described, the IGBT 153 has such a structure that the N.sup.+ layer 201 is just replaced with a two-layer structure formed by the p.sup.+ layer 301 and the N.sup.+ buffer layer 311 in the MOS 151.
This IGBT 153 operates as follows: First, a collector voltage V.sub.CE of prescribed magnitude is applied between the collector electrode 312 and the emitter electrode 310 so that the side of the collector electrode 312 is positive. When applying a gate voltage V.sub.GE exceeding a gate threshold voltage V.sub.GE (th) (turning on a gate) so that the side of the gate electrode 308 is positive, the p-type channel regions 306 are inverted to an n type and n-type channels are formed in the channel regions 306.
Through these channels, electrons are injected from the emitter electrode 310 into the n.sup.- layer 302. The p.sup.+ layer 301 and the n.sup.- layer 302 (including the N.sup.+ buffer layer 311) are forward-biased by the injected electrons, and holes are injected from the p.sup.+ layer 301. Consequently, the resistance of the n.sup.- layer 302 remarkably lowers, and a large main current flows from the collector electrode 312 to the emitter electrode 310. Namely, the IGBT 153 enters an ON state. Thus, the IGBT 153 lowers the resistance of the n.sup.- layer 302 by injection of the holes from the p.sup.+ layer 301.
Then, when inverting the gate voltage V.sub.GE from the positive value to the value of zero or a negative (reverse bias) value (turning off the gate) in the state applying the collector voltage V.sub.CE, the channel regions 306 having been inverted to the n type return to the original p type. Consequently, the injection of the electrons from the emitter electrode 310 into the n.sup.- layer 302 stops. Following this, the injection of the holes from the p.sup.+ layer 301 into the n.sup.- layer 302 also stops. Thereafter the electrons and the holes having been stored in the n.sup.- layer 302 (including the N.sup.+ buffer layer 311) escape toward the collector electrode 312 and the emitter electrode 310 respectively, or disappear by coupling with each other. Thus, the IGBT 153 enters an OFF state.
As hereinabove described, each of the MOS 151, the BIP 152 and the IGBT 153 controls the main current in response to the voltage or the current applied to a control electrode (i.e., the gate electrode or the base electrode).
These three types of transistors had characteristics described below. FIG. 40 is a graph showing output characteristics of these three types of transistors with rated voltages in the range of about 200 V to about 500 V. Referring to FIG. 40, the horizontal axis corresponds to the voltages (i.e., the collector voltages V.sub.CE) between the pairs of main electrodes, and the vertical axis corresponds to the main currents. In the MOS 151, an ON-state voltage rises when the main current increases. Further, such a point that the magnitude of the main current is small as compared with the remaining transistors is characteristic.
In the IGBT 153, the main current is large, while such a characteristic is recognized that an ON-state voltage in the low current range is large. On the other hand, the BIP 152 exhibits such a characteristic that the main current is large and moreover an ON-state voltage is low. Namely, it can be said that the BIP 152 is most excellent in relation to the output characteristics.
FIG. 41 is a graph showing turn-off characteristics of the three types of transistors similarly with rated voltages in the range of about 200 V to about 500 V. Referring to FIG. 41, the horizontal axis corresponds to elapsed times, and the vertical axis corresponds to the magnitude of the main currents in the process of transition from ON states to OFF states. In the BIP 152 which is most excellent in the output characteristics, the turn-off time lengthens to about 10 times the MOS 151. Comparing the MOS 151 and the IGBT 153 with each other, there is no large difference although the turn-off time of the MOS 151 is short to some extent.
As hereinabove described, there has been such a problem that the ON-state voltages are high in the MOS and the IGBT, and there has been such a problem that the turn-off time is long in the BIP among the conventional three types of power transistors. A transistor whose ON-stage voltage is low, which is simultaneously excellent in turn-off characteristic has not been known in general.